1. Field of the Invention
The present invention relates to a technology effective for the device testing of semiconductor memory devices.
2. Description of the Prior Art
The testing of a semiconductor memory device such as a dynamic random access memory (DRAM) and the analysis of its defective bits are performed by connecting each of the input and output pins of the semiconductor memory device to a memory tester to write data to and read data from each of individual memory cells of the semiconductor memory device.
Recent enhancement of the memory capacity (an increase in the number of the memory cells) of the semiconductor memory device due to progress in technology has significantly increased the cost of testing the device. Typically, in order to reduce the cost, a circuit dedicated only to testing but not used for ordinary operations is built into the semiconductor memory device.
Further, particularly in the DRAM market, demand of multiple bits has been strong, and the multiple bits of x8 and x16 are the main stream of the current DRAM market. The multiple bit technology causes an increase in the number of pins of the device, which, in turn, causes an increase in the number of pins of the tester. If the device has more pins according to the multiple bit technology, the tester will test a lesser number of devices per unit time if the tester has a fixed number of pins, thus resulting in a higher cost of testing. One solution for this problem is to build a circuit in the device which is dedicated to testing and is capable of degenerating four input/output pins, for example, to one pin. That is, if the device is x16, this circuit makes the device look as if it is an x4 device. The device with this circuit therein, therefore, can be tested four times as fast as the device without this circuit and, accordingly, very economically.
The memory cells of the aforementioned semiconductor memory device are built densely packed so that the area of the chip is minimal. Accordingly, physical bit positions in the chip and the data stored there have no direct sequential correspondence to logical address values and logical data values provided from an external device. However, in actual testing it is often desirable to store data at a specified physical memory address. In order to negotiate the difference between the logical values and the physical values, the address scramble and the data scramble processes are often performed. Typically a memory tester is equipped with a software program for the address scramble and the data scramble processes. The memory tester equipped with this kind of software program performs the scramble process appropriate to the tested chip, provides signals processed by the scramble process to the device, and carries out a physical test on the device and analyzes the resulting data.
However, the semiconductor memory device equipped with the circuit which is dedicated to testing and reduces four input/output pins into one pin can not be tested with an external tester which scrambles data using the software, if the data scramble logic to be processed by the four input/output pins are not the same. Because the data cannot be written to or read from a desired physical address.